As a first step in testing an integrated circuit chip probe contact to the chip is usually checked to ensure that good electrical connection has been achieved. FIG. 1a shows a circuit diagram and FIG. 1b shows a cross sectional view of an inverter type of input receiver 18 on a chip formed on a conventional bulk silicon semiconductor wafer. Input pad 20 of integrated circuit chip 22 is connected to gates 24a, 24b of inverter pair 26 of complementary CMOS transistors, including PFET 28a and NFET 28b that make up receiver 18. Input pad 20 and gates 24a, 24b are also connected to diffusion 30 in p-substrate substrate 32 that forms ESD protect diode 34. Probe contact to input pad 20 of chip 22 is easily checked by a technique such as forcing a voltage between pad and substrate probes (not shown) to forward bias protect diode 34, and measuring the resulting current at either probe. Where chip pads on bulk silicon substrates are connected to semiconductor substrate 32 through a diffusion such as diffusion 30 of ESD protect diode 34, contact is most easily checked by looking for the current-voltage characteristic of a forward biased diode between chip pad 10 and substrate 32.
However. some semiconductor technologies save chip real estate by providing inputs without protect devices, and these technologies have essentially floating gates, making the contact check difficult. Other technologies use protect devices that are not easily turned on, such as snap back diodes, and this similarly hinders the contact check. In addition, devices fabricated on material having a back insulator, such as SOI CMOS pair 40 of FIG. 2, are isolated from semiconductor substrate 32 by back insulator 42. CMOS SOI transistors 24a' and 24b' are formed in isolated wells 44a, 44b, and there is generally no well contact brought out. Input pad 20' of the SOI chip is therefore not electrically connected to another available pad through a device, such as a resistor or diffusion, that would enable checking probe contact.
In cases where there has been no diode to forward bias or where no substantial current could be forced between an input pad and the substrate or between any other two pads, there has been no way to distinguish probe contact difficulties from internal causes of chip failure. The solution to this uncertainty has been to simply push harder on the probes and test again. However, a better solution is needed that provides a way to check whether probes are properly electrically connected to chip pads and to determine which of the many probes is not electrically connected, and this solution is provided by the following invention.